Name
Abstract | ||
|---|---|---|
The routing architecture, heavily using programmable switches, dominates the area, delay and power of Field Programmable Gate Arrays (FPGAs). Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs, RRAM-based routing multiplexers can be used to significantly reduce the FPGA routing delays. In addition, RRAM-based routing architectures are less sensitive to supply voltage reductions and show promises in low-power FPGA designs. In this paper, we propose a near-Vt low-power RRAM-based FPGA where both delay and power reductions are achieved. Experimental results demonstrate that a near-Vi RRAM-based FPGA design leads to a 15% area shrink, a 10% delay reduction, and a 65% power improvement, compared to a conventional FPGA design for a given technology node. To achieve low on-resistance values, RRAMs typically require high programming currents. In other word, they need relatively large programming transistors, potentially resulting in area, delay and power inefficiencies. We also present a design methodology to properly size the programming transistors of RRAMs in order to further improve the area-efficiency. Experimental results show that a correct programming transistor sizing strategy contributes to further 18% area and 2% delay shrink, compared to the initial near-Vi RRAM-based FPGA. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPT.2014.7082777 | FPT |
Keywords | Field | DocType |
rram-based fpga,network routing,programmable switches,resistive ram,routing architecture,sram chips,low-power electronics,fpga routing delays,routing multiplexers,static random access memory,resistive random access memories,sram-based programming switches,field programmable gate arrays,low-power near-vt | Computer science,Resistive touchscreen,Voltage,Parallel computing,Field-programmable gate array,Static random-access memory,Real-time computing,Multiplexer,Transistor,Random access,Resistive random-access memory | Conference |
Citations | PageRank | References |
4 | 0.47 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xifan Tang | 1 | 59 | 12.89 |
| Pierre-Emmanuel Gaillardon | 2 | 355 | 55.32 |
| Giovanni De Micheli | 3 | 10245 | 1018.13 |