Paper Info
Title
Fault resilient physical neural networks on a single chip
Abstract
Device scaling engineering is facing major challenges in producing reliable transistors for future electronic technologies. With shrinking device sizes, the total circuit sensitivity to both permanent and transient faults has increased significantly. Research for fault tolerant processors has primarily focused on the conventional processor architectures. Neural network computing has been employed to solve a wide range of problems. This paper presents a design and implementation of a physical neural network that is resilient to permanent hardware faults. To achieve scalability, it uses tiled neuron clusters where neuron outputs are efficiently forwarded to the target neurons using source based spanning tree routing. To achieve fault resilience in the face of increasing number of permanent hardware failures, the design pro-actively preserves neural network computing performance by selectively replicating performance critical neurons. Furthermore, the paper presents a spanning tree recovery solution that mitigates disruption to distribution of neuron outputs caused by failed neuron clusters. The proposed neuron cluster design is implemented in Verilog. We studied the fault resilience performance of the described design using a RBM neural network trained for classifying handwritten digit images. Results demonstrate that our approach can achieve improved fault resilience performance by replicating only 5% most important neurons.
Year
DOI
Venue
2014
10.1145/2656106.2656126
CASES
Keywords
Field
DocType
design,handwritten digit images classification,network routing,experimentation,permanent hardware faults,microprocessor chips,trees (mathematics),verilog,device scaling engineering,total circuit sensitivity,hardware description languages,fault tolerant processors,neuron outputs,rbm neural network,performance critical neurons,device sizes shrinking,measurement,electronic technologies,fault diagnosis,spanning tree recovery solution,permanent hardware failures,single chip,tiled neuron clusters,fault resilient physical neural networks,neural network computing,processor architectures,transient faults,source based spanning tree routing,fault resilience performance,transistors,performance,neural nets,real-time and embedded systems,neural chips,routing,hardware,reliability,neural networks,modeling,compiler
Physical neural network,Computer science,Parallel computing,Real-time computing,Compiler,Chip,Fault tolerance,Spanning tree,Verilog,Artificial neural network,Scalability
Conference
ISSN
Citations 
PageRank 
2381-1560
2
0.35
References 
Authors
37
7
Name
Order
Citations
PageRank
Weidong Shi133141.44
Yuanfeng Wen2687.99
Ziyi Liu3394.18
Xi Zhao432025.40
Dainis Boumber581.95
Ricardo Vilalta630.78
Lei Xu73617.39