Name
Abstract | ||
|---|---|---|
In this paper a high-throughput FPGA implementation of a Volterra-based Decision Feedback Equalizer (DFE) is presented for first time. The DFE is a popular scheme, and its performance is a critical issue in high-speed communication systems. To overcome the throughput limitation due to the feedback loop, two multiplexer-based architectures were developed and compared. The introduced architectures were implemented on two Xilinx FPGAs, exploiting the specific features of these devices. Based on the experimental results, it is proved that the introduced designs achieve high throughput (10Gb/s), showing that the FPGAs are a suitable option for high-speed systems (e.g. optical communication systems). |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2645791.2645831 | Panhellenic Conference on Informatics |
Keywords | Field | DocType |
design,fpga,volterra filter,decision feedback equalizer,gate arrays | Equalizer,Computer science,Optical communication,Field-programmable gate array,Communications system,Multiplexer,Feedback loop,Real-time computing,Throughput,Fpga implementations | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andreas Emeretlis | 1 | 11 | 2.95 |
| george theodoridis | 2 | 67 | 14.19 |