Paper Info
Title
Analytical method for reliability assessment of concurrent checking circuits under multiple faults
Abstract
Reliability issues due to transient faults have increased with CMOS scaling and become an important concern for deep submicron technologies. Concurrent Error Detection (CED) scheme has been widely used against transient faults under the assumption of single fault and/or fault-free checking parts. In this work, we propose an analytical method in order to assess CED circuit reliability under more realistic hypothesis. In other words, we take into account the occurrence of multiple faults and fault-prone checking parts. This method allows to demonstrate the efficiency of CED schemes. The computational requirements for such an assessment are reduced by progressive analysis of the overall circuit through conditional probabilities. The proposed solution has been demonstrated on classical CED schemes.
Year
DOI
Venue
2014
10.1109/MIPRO.2014.6859532
MIPRO
Keywords
Field
DocType
concurrent error detection scheme,cmos integrated circuits,computational requirements,transients,integrated circuit reliability,error detection,cmos scaling,ced circuit reliability,concurrent checking circuits,fault-prone checking parts,analytical method,computational complexity,ced scheme,deep submicron technologies,fault diagnosis,multiple faults,reliability assessment,progressive analysis,transient faults,fault-free checking parts,reliability issues,probability,logic gates,adders
Conditional probability,Computer science,Circuit reliability,Computer network,Concurrent checking,Error detection and correction,Real-time computing,Cmos scaling,Electronic circuit,Reliability engineering
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Ting An153.52
Kaikai Liu219020.37
Lirida A. B. Naviner38326.52