Name
Abstract | ||
|---|---|---|
This paper introduces a new FoM (figure of merit) to evaluate the overall performance of ESD and LNA and presents a design procedure of establishing a standard library of ESD protection cells to reduce the design time and complexity for RFIC designer. The electrostatic discharge protection cells have been designed in a 0.35μm BiCMOS process. The ESD robustness and RF characteristics will be verified when the RF chip is done. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASICON.2013.6812038 | ASICON |
Keywords | Field | DocType |
lna,low noise amplifiers,rfic,bicmos analogue integrated circuits,radiofrequency integrated circuits,figure of merit,esd protection,size 0.35 mum,electrostatic discharge protection,integrated circuit design,electrostatic discharge,bicmos process,fom | Electrostatic discharge protection,Co-design,Computer science,Robustness (computer science),Chip,Electronic engineering,Figure of merit,Bicmos process,RFIC,Electrical engineering | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-4673-6415-7 | 0 |
PageRank | References | Authors |
0.34 | 1 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yueguo Hao | 1 | 0 | 0.34 |
| Qiao Zhang | 2 | 0 | 0.34 |
| Xiaopeng Bai | 3 | 0 | 0.34 |
| Z. T. Shi | 4 | 21 | 3.72 |
| Huainan Ma | 5 | 0 | 0.34 |
| Yuhua Cheng | 6 | 33 | 6.82 |