Name
Abstract | ||
|---|---|---|
A high performance VLSI architecture for integer motion estimation (IME) in High Efficiency Video Coding (HEVC) is presented in this paper. It supports coding tree block (CTB) structure with the asymmetric motion partition (AMP) mode. The architecture contains two parallel sub-architectures to meet 1080p@30fps real-time video coding. The size LxL of CTB in the architecture is set to L=32 pixels by default, and it can be extended to L=64 and L=16 pixels. A serial mode decision module to find optimal partition mode for the architecture has also been implemented. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASICON.2013.6811845 | ASICON |
Field | DocType | Citations |
Architecture,Quarter-pixel motion,Coding tree unit,Computer science,Coding (social sciences),Real-time computing,Electronic engineering,Pixel,Partition (number theory),Integer motion estimation,Vlsi architecture | Conference | 5 |
PageRank | References | Authors |
0.46 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuan Xu | 1 | 20 | 3.33 |
| Jinsong Liu | 2 | 5 | 0.46 |
| Liwei Gong | 3 | 5 | 0.46 |
| Zhi Zhang | 4 | 5 | 0.46 |
| Robert K. F. Teng | 5 | 6 | 1.54 |