Title
An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm
Abstract
An FPGA implementation of an all-digital fully compliant IEEE 802.11b and 802.15.4 configurable baseband receiver is presented. This architecture can be integrated in systems implementing the Software Defined Radio (SDR) paradigm, relaxing the need for high power consumption general purpose processors. The receiver uses a single architecture that can be configured for receiving either standard at run time, exploiting similarities between both protocols, and may serve as a coprocessor for offloading the task of processing baseband RF signals. The system can be used as a platform for future low power devices to integrate into the SDR paradigm. Results showed that the architecture exceeds the specifications required by both standards, and has great performance in low SNR scenarios, making it an attractive alternative in wireless sensor networks with extremely low signal power levels.
Year
DOI
Venue
2014
10.1109/ReConFig.2014.7032499
ReConFigurable Computing and FPGAs
Keywords
Field
DocType
Zigbee,field programmable gate arrays,power consumption,protocols,radio receivers,software radio,telecommunication power management,wireless LAN,FPGA implementation,all-digital 802.11b receiver,all-digital 802.15.4 receiver,baseband RF signals,configurable baseband receiver,coprocessor,power consumption,protocols,software defined radio paradigm,FPGA,QPSK,Software Defined Radio,VLSI,WiFi,ZigBee,digital receivers,reconfigurable receiver
Baseband,Radio receiver design,Software-defined radio,Computer science,Field-programmable gate array,Radio frequency,Real-time computing,Coprocessor,Wireless sensor network,Phase-shift keying,Embedded system
Conference
ISSN
Citations 
PageRank 
2325-6532
0
0.34
References 
Authors
5
9