Name
Abstract | ||
|---|---|---|
Design constraints describe the intent of IC designers when developing electronic circuits. Constraints from, e.g., electrical and thermal domains are transformed into corresponding physical constraints for layout design. Physical constraints can also be derived from circuit patterns or extracted layout netlists. The constraint verification is of utmost importance to guarantee the intended function of the final IC. Individual constraints often span multiple hierarchy levels, thus requiring a fully hierarchical verification approach. A novel, modular, and extensible industrial-strength approach is presented to (1) derive analog-focused design constraints from an existing circuit or extracted layout netlist, and (2) verify analog constraints such as clustering, matched orientation, matched parameters, alignment, and symmetry across multiple design hierarchy levels. Experimental results for real-world automotive IC designs demonstrate its feasibility. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASPDAC.2015.7059047 | ASP-DAC |
Field | DocType | ISSN |
Formal equivalence checking,Integrated circuit layout,Netlist,Layout Versus Schematic,Computer science,Physical verification,IC layout editor,Real-time computing,Electronic engineering,Design layout record,Physical design | Conference | 2153-6961 |
Citations | PageRank | References |
2 | 0.44 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Volker Meyer zu Bexten | 1 | 2 | 0.44 |
| Markus Tristl | 2 | 2 | 0.44 |
| Göran Jerke | 3 | 34 | 5.19 |
| Hartmut Marquardt | 4 | 2 | 0.44 |
| Dina Medhat | 5 | 2 | 0.44 |