Name
Abstract | ||
|---|---|---|
The short time to market cycle and the target to reduce design and verification costs are driving forces to design programmable implementations of the video processing algorithms. We present two processor architectures the first one representing an application-specific instruction set processor (ASIP) design, whereas the second architecture represents a domain-specific instruction-set processor (DSIP) architecture with more general purpose instruction-set. In this work, we present results for H264 and VP8 in-loop deblocking algorithms. The processors are based on the transport triggered architecture which provides scalable instruction-level parallelism and, thanks to its simple structure, lend itself to cost effective designs. Both of the designs are programmed with C language with a minimal additional parallelism markup. The designs fulfill realtime requirements for filtering macroblocks in high-definition video. The first architecture, based on special function units, filters a high-definition stream (1920 × 1080) at 75 fps, whereas the second architecture, which provides a better programmability, filters the stream at 53 fps. The processors run on 200 MHz clock frequency and the areas vary from 146k to 373k gate equivalents depending on the processor architecture. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SiPS.2014.6986071 | SiPS |
Keywords | Field | DocType |
high definition video,vp8 in-loop deblocking algorithms,video decoders,domain specific instruction set processor architecture,c language,transport triggered architecture,instruction-level parallelism,programmability,video coding,instruction sets,asip design,programmable filters,application specific instruction set processor,dsip architecture,high definition stream,programmable in-loop deblock filter processor,video processing algorithms | Video processing,Application-specific instruction-set processor,Computer architecture,Computer science,Instruction set,Parallel computing,Transport triggered architecture,Real-time computing,Clock rate,Deblocking filter,Microarchitecture,Scalability | Conference |
Citations | PageRank | References |
1 | 0.35 | 8 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Janne Janhunen | 1 | 86 | 11.81 |
| Pekka Jääskeläinen | 2 | 140 | 31.26 |
| Jari Hannuksela | 3 | 121 | 13.36 |
| Tero Rintaluoma | 4 | 14 | 2.61 |
| Aki Kuusela | 5 | 13 | 0.79 |