Title
Design space exploration of multiple loops on FPGAs using high level synthesis
Abstract
Real-world applications such as image processing, signal processing, and others often contain a sequence of computation intensive kernels, each represented in the form of a nested loop. High-level synthesis (HLS) enables efficient hardware implementation of these loops using high-level programming languages. HLS tools also allow the designers to evaluate design choices with different trade-offs through pragmas/directives. Prior design space exploration techniques for HLS primarily focus on either single nested loop or multiple loops without consideration to the data dependencies among them. In this paper, we propose efficient design space exploration techniques for applications that consist of multiple nested loops with or without data dependencies. In particular, we develop an algorithm to derive the Pareto-optimal curve (performance versus area) of the application when mapped onto FPGAs using HLS. Our algorithm is efficient as it effectively prunes the dominated points in the design space. We also develop accurate performance and area models to assist the design space exploration process. Experiments on various scientific kernels and real-world applications demonstrate that our design space exploration technique is accurate and efficient.
Year
DOI
Venue
2014
10.1109/ICCD.2014.6974719
ICCD
Keywords
Field
DocType
high-level programming languages,signal processing,image processing,pareto-optimal curve,logic design,fpga,field programmable gate arrays,high-level synthesis,high level synthesis
Design space,Signal processing,Computer science,High-level synthesis,Parallel computing,Field-programmable gate array,Image processing,Real-time computing,Design space exploration,Computation,Nested loop join
Conference
ISSN
Citations 
PageRank 
1063-6404
14
0.84
References 
Authors
14
5
Name
Order
Citations
PageRank
Guanwen Zhong1393.43
Vanchinathan Venkataramani2765.85
Yun Liang386859.55
Tulika Mitra42714135.99
Smaïl Niar57523.58