Paper Info
Title
Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture
Abstract
Due to the need to support concurrent executions of versatile applications, the system complexity, in terms of the number of cores, is drastically increased from tens to hundreds or thousands of cores. These complex systems usually contain heterogeneous cores or processing elements such as different processor cores, memories, and several Silicon Intellectual Properties (SIPs). Network-on-chip (NoC) was proposed to provide scalability and higher throughput for these heterogeneous multi-core systems. However, general designs of NoC infrastructures for multi-core systems usually lack the flexibility to support different processing requirements such as performance, power, reliability, and response time. It is helpful if designers can provide a reconfigurable NoC design so that these requirements can be supported more easily. In this work, we take an existing reconfigurable NoC for example and discuss related hardware and software issues. Some issues such as the reconfiguration time overhead must be considered in the design of a reconfigurable NoC such that it can be used for heterogeneous multi-core systems.
Year
DOI
Venue
2014
10.1109/HPCSim.2014.6903730
HPCS
Keywords
Field
DocType
reconfigurable network-on-chip design,reconfigurable architectures,concurrent executions,adaptive routing,multiprocessing systems,heterogeneous multicore system architecture,sip,hardware interface,network-on-chip,silicon intellectual properties,noc,hardware/software co-design,reconfiguration
Computer architecture,Computer science,Parallel computing,Network on a chip,Systems architecture,Multi-core processor,Network on chip design,Hardware architecture,Embedded system
Conference
Citations 
PageRank 
References 
2
0.36
9
Authors
3
Name
Order
Citations
PageRank
Jih-Sheng Shen1918.53
Pao-ann Hsiung262468.75
Juin-Ming Lu341.49