Name
Abstract | ||
|---|---|---|
In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPL.2014.6927429 | FPL |
Keywords | Field | DocType |
performance gain,clustering algorithm,statistical analysis,pattern-based fpga logic block,large control-instensive benchmarks,wirelength reduction,field programmable gate arrays,routing,clustering algorithms,bismuth | Architecture,Computer science,Parallel computing,Programmable logic array,Field-programmable gate array,Logic block,Cluster analysis | Conference |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xifan Tang | 1 | 59 | 12.89 |
| Pierre-Emmanuel Gaillardon | 2 | 355 | 55.32 |
| Giovanni De Micheli | 3 | 10245 | 1018.13 |