Name
Abstract | ||
|---|---|---|
Dual-output lookup tables (LUTs) are mainstream in the design of commercial FPGA products. A detailed exploration of architectural parameters of FPGAs based on dualoutput LUTs is presented. Different from traditional single-output LUT based architecture, “shared inputs” between the sub-LUTs is a new parameter specific to dual-output architecture. In this paper, we focus on the effect of ratio of shared inputs on the performance and area-efficiency. First, we study the required cluster inputs and derive a relationship between cluster inputs, LUT size and cluster size under different ratios of shared inputs. Secondly, our evaluation results show that a FPGA with 4-LUTs and a shared input ratio of two thirds is preferred for area-efficiency, while a large LUT size of 9 with no shared inputs achieves best performance. Finally, we determine that a LUT size of 4, a cluster size from 3 to 8, and a shared input ratio between 1/3 and 2/3, provide the best area-delay product for dual-output LUT based FPGAs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPL.2014.6927470 | FPL |
Keywords | Field | DocType |
dual-output lookup tables,area efficiency,cluster inputs,dual-output lut,fpga,architectural parameters,field programmable gate arrays,architecture parameters,area-delay product,table lookup | Lookup table,Architecture,Computer science,Parallel computing,Field-programmable gate array,Real-time computing | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenghong Jiang | 1 | 4 | 2.16 |
| Colin Lin Yu | 2 | 28 | 6.42 |
| Liqun Yang | 3 | 9 | 1.27 |
| Fei Wang | 4 | 125 | 45.09 |
| Haigang Yang | 5 | 34 | 16.84 |