Paper Info
Title
Hardware system synthesis from Domain-Specific Languages
Abstract
Field Programmable Gate Arrays (FPGAs) are very versatile devices, but their complicated programming model has stymied their widespread usage. While modern High-Level Synthesis (HLS) tools provide better programming models, the interface they offer is still too low-level. In order to produce good quality hardware designs with these tools, the users are forced to manually perform optimizations that demand detailed knowledge of both the application and the implementation platform. Additionally, many HLS tools only generate isolated hardware modules that the user still needs to integrate into a system design before generating the FPGA bitstream. These problems make HLS tools difficult to use for application developers who have little hardware design knowledge. To address these problems, we propose an automated methodology to generate FPGA bitstreams from high-level programs written in Domain-Specific Languages (DSLs). We leverage the domain-knowledge conveyed by the DSL and its domain-specific semantics to extract application parallelism, perform optimizations and also identify a suitable system-architecture for the implementation, thereby, relieving the user from most of the hardware-level details. We demonstrate the high productivity and high design quality this approach offers by automatically generating hardware systems from applications written in OptiML, a machine-learning DSL. To evaluate our methodology, we use four OptiML applications and show that we can easily generate different solutions which achieve different trade-offs between performance and area. More importantly, the results reveal that our generated hardware achieves much better performance compared to the one obtained from using the HLS tool without platform-specific optimizations.
Year
DOI
Venue
2014
10.1109/FPL.2014.6927454
Field Programmable Logic and Applications
Keywords
Field
DocType
field programmable gate arrays,learning (artificial intelligence),logic design,specification languages,FPGA bitstream,FPGAs,HLS tools,OptiML,application parallelism extraction,complicated programming model,domain-specific languages,domain-specific semantics,field programmable gate arrays,hardware system synthesis,hardware-level details,high-level programs,isolated hardware modules,machine-learning DSL,quality hardware designs,system design,system-architecture
Domain-specific language,Data structure,Design knowledge,Hardware compatibility list,Programming paradigm,Computer science,Systems design,Field-programmable gate array,Real-time computing,Computer hardware,Embedded system,Reconfigurable computing
Conference
Citations 
PageRank 
References 
20
0.88
20
Authors
9
Name
Order
Citations
PageRank
Nithin George1384.08
HyoukJoong Lee241417.71
David Novo317712.58
Tiark Rompf474345.86
Kevin J. Brown544818.62
Arvind K. Sujeeth650220.58
Martin Odersky72261170.39
Kunle Olukotun84532373.50
Paolo Ienne92246199.26