Name
Abstract | ||
|---|---|---|
A 50-GHz charge pump phase locked loop (PLL) utilizing an LC-oscillator based injection locked divider is fabricated in a 130-nm logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers consumes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/CICC.2006.320940 | CICC |
Keywords | Field | DocType |
45.9 to 50.5 ghz,cmos integrated circuits,nanotechnology,1 mhz,50 khz,10 mhz,1.5 v,charge pump,logic cmos process,57 mw,phase locked loops,0.8 v,phase-locked loop,buffer circuits,buffers,phase noise,130 nm,91.8 to 101 ghz,second order harmonic frequencies,lc-oscillator based injection locked divider,millimetre wave integrated circuits,oscillations,phase lock loop,second order,injection locking | Phase-locked loop,Frequency divider,Computer science,Harmonic,Phase noise,Electronic engineering,CMOS,Voltage-controlled oscillator,dBc,Electrical engineering,Integrated circuit | Conference |
ISBN | Citations | PageRank |
1-4244-0076-7 | 13 | 2.61 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Cao | 1 | 92 | 14.45 |
| Yanping Ding | 2 | 41 | 7.00 |
| Kenneth K. O | 3 | 249 | 42.87 |