Name
Abstract | ||
|---|---|---|
This paper presents a method to model the drain current of LDMOS working in the 3rd quadrant (Vds<;0), which is important for power management IC design. The DIBL effect in 3rd quadrant is shown to be much more significant than that in 1st quadrant (Vds>0), and is not captured by the existing LDMOS models. Also, the threshold voltage model is not accurate in 3rd quadrant, where the drain-body junction is forward biased. Consequently, the existing LDMOS models underestimate the 3rd quadrant drain current in the sub-threshold region. A drain current expression taking into account these effects for the sub-threshold region is developed and added to the device model through a SPICE component bsource. The modeling accuracy of the drain current in the 3rd quadrant is significantly improved. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/CICC.2014.6946028 | CICC |
Keywords | Field | DocType |
subthreshold region,drain-induced barrier lowering effect,semiconductor device models,drain-body junction,spice,power management ic design,integrated circuit modelling,simulation,power mosfet,spice component bsource,laterally diffused metal oxide semiconductor,integrated circuit design,semiconductor device modeling,mosfet circuits,third quadrant drain current,mosfet,ldmos compact modeling,threshold voltage model,dibl effect,forward bias,modeling accuracy | Quadrant (instrument),LDMOS,Power semiconductor device,Computer science,Semiconductor device modeling,Electronic engineering,Electrical engineering,Drain-induced barrier lowering | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kejun Xia | 1 | 0 | 0.34 |
| Harihara Indana | 2 | 0 | 0.34 |
| Usha Gogineni | 3 | 0 | 0.34 |