Name
Abstract | ||
|---|---|---|
Extracting data paths in large-scale registertransfer level designs has important usage in automatic verification of synchronous circuits and synthesis of asynchronous circuits. Current tools rely on users to provide the data/control partition or use state-space analyses to extract data paths. Due to the explosion of state-space, the latter method can be used in only small designs. To resolve this problem, a graphic search and trim method, which can extract data paths in large scale designs, is presented. A design is first translated into a graphic representation, namely a signal-level data flow graph (DFG), to reveal the connections between signals. By estimating the types (control or data) of these connections, a linear search algorithm can then remove all control-related signals in the graph, which effectively produces a DFG with pure data paths. Results show that this method extracts data paths of large scale designs in seconds. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCAS.2014.6865144 | ISCAS |
Keywords | Field | DocType |
linear search algorithm,registers,data mining,decoding,hardware,logic design,formal verification | Logic synthesis,Asynchronous communication,Pure Data,Computer science,Algorithm,Data-flow analysis,Register-transfer level,Decoding methods,Linear search,Formal verification | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Song | 1 | 25 | 4.25 |
| Jim D. Garside | 2 | 350 | 33.15 |
| Doug A. Edwards | 3 | 5 | 1.32 |