Paper Info
Title
A 2+1 multi-bit incremental architecture using Smart-DEM algorithm
Abstract
This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%).
Year
DOI
Venue
2014
10.1109/ISCAS.2014.6865473
ISCAS
Keywords
Field
DocType
multibit incremental architecture,analogue-digital conversion,third order incremental analog-digital architecture,operational amplifiers,operational amplifier output swing,smart-dem algorithm,multibit quantization
Architecture,Control theory,Computer science,PLL multibit,Electronic engineering
Conference
ISSN
Citations 
PageRank 
0271-4302
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Liu Yao13112.05
Edoardo Bonizzoni216247.30
Franco Maloberti3686144.70