Paper Info
Title
Area and throughput efficient IDCT/IDST architecture for HEVC standard.
Abstract
High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4x4 to 32x32 pixels as well as 4x4 pels IDST. Using 65nm technology, the synthesis results show that the maximum work frequency is 500MHz and the architecture hardware cost is about 145.4K gate count. Compared with previous work, our design achieves more than 50% reduction in hardware cost and 66% improvement in throughput efficiency. Experimental results show that the proposed architecture is able to deal with real-time HEVC IDCT/IDST of 4Kx2K (4096x2048)@30 fps video sequence at 412MHz in average. In consequence, it offers a cost-effective solution for the future UHDTV applications.
Year
DOI
Venue
2014
10.1109/ISCAS.2014.6865683
ISCAS
Keywords
DocType
ISSN
scheduling,vlsi,computer architecture,throughput,hardware,real time systems
Conference
0271-4302
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
Ziyou Yao100.34
Weifeng He26114.69
Liang Hong319333.79
Guanghui He48012.73
Zhigang Mao519941.73