Name
Abstract | ||
|---|---|---|
In this paper we present the design of a wireless power receiver fully integrated. The circuit was constrained to occupy a silicon area of 1.5 mm × 1.5 mm in a 0.18 μm RF-CMOS process. The main target was to optimize the part of the power transfer efficiency concerning only the receiver side. In that way, we optimized the quality factor of the integrated inductor, the impedance matching conditions and the rectifier efficiency. The simulated quality factor of the integrated inductor was 22 using a link frequency of 1 GHz. Post-layout simulations of the entire system shows that the combined efficiency of the impedance matching network and the rectifier is 57% when the available power at the inductor is 1 dBm. Moreover, the system uses backscattering to respond to the transmitter, allowing to infer the total power transfer efficiency. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCAS.2014.6865408 | Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,elemental semiconductors,impedance matching,integrated circuit design,radio receivers,radio transmitters,radiofrequency integrated circuits,rectifiers,silicon,RF-CMOS,Si,autonomous implanted devices,frequency 1 GHz,impedance matching network,quality factor,rectifier,size 0.18 mum,size 1.5 mm,total power transfer efficiency,transmitter,wireless power receiver | Transmitter,Q factor,Rectifier,Computer science,Impedance matching,Inductor,CMOS,Electronic engineering,Integrated circuit design,Maximum power transfer theorem,Electrical engineering | Conference |
ISSN | Citations | PageRank |
0271-4302 | 2 | 0.44 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fabian L. Cabrera | 1 | 4 | 1.87 |
| Fernando Rangel de Sousa | 2 | 43 | 12.99 |
| Rangel de Sousa, F. | 3 | 2 | 0.44 |