Name
Abstract | ||
|---|---|---|
The advanced encryption standard (AES) has been sufficiently studied to confirm that its decryption is computationally impossible. However, its vulnerability against fault analysis attacks has been pointed out in recent years. To verify the vulnerability of electronic devices in the future, into which cryptographic circuits have been incorporated, fault Analysis attacks must be thoroughly studied. The present study proposes a new fault analysis attack method which utilizes the tendency of an operation error due to a glitch. The present study also verifies the validity of the proposed method by performing evaluation experiments using FPGA. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SNPD.2014.6888689 | 2014 15TH IEEE/ACIS INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING, ARTIFICIAL INTELLIGENCE, NETWORKING AND PARALLEL/DISTRIBUTED COMPUTING (SNPD) |
Keywords | Field | DocType |
Fault analysis attacks, Error value, Tamper resistance, Side-channel attack | Watermarking attack,Power analysis,Fault analysis,Computer science,Distributed computing,Differential fault analysis | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masaya Yoshikawa | 1 | 25 | 23.93 |
| Hikaru Goto | 2 | 0 | 0.34 |
| Kensaku Asahi | 3 | 1 | 3.78 |