Name
Abstract | ||
|---|---|---|
In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ACSSC.2014.7094504 | Pacific Grove, CA |
Keywords | Field | DocType |
channel coding,decoding,iterative methods,parity check codes,random-access storage,turbo codes,LDPC channel decoder architecture,decoding process,faulty memory bit-cells,inherent error resilience,memory fault impact reduction,mitigation mechanism,realistic memory failure model,repair-iterations,turbo channel decoder architecture | Turbo,Concatenated error correction code,Sequential decoding,Computer science,Low-density parity-check code,Turbo code,Serial concatenated convolutional codes,Electronic engineering,Turbo equalizer,Soft-decision decoder | Conference |
ISSN | Citations | PageRank |
1058-6393 | 2 | 0.45 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joao Andrade | 1 | 52 | 8.51 |
| Aida Vosoughi | 2 | 109 | 8.51 |
| Guohui Wang | 3 | 1088 | 60.78 |
| Georgios Karakonstantis | 4 | 317 | 37.08 |
| A. Burg | 5 | 1426 | 126.54 |
| Gabriel Falcão | 6 | 64 | 16.36 |
| Vítor Manuel Mendes Da Silva | 7 | 214 | 24.47 |
| Joseph R. Cavallaro | 8 | 1175 | 115.35 |