Abstract | ||
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The high-density blade server provides an attractive solution for the rapid increasing demand on computing. The degree of parallelism inside a blade enclosure nowadays has reach up to hundreds of cores. In such parallelism, it is necessary to accelerate communications inside a blade enclosure. However, commercial products seldom set foot in the optimization based on hardware. A hyper-node controller is proposed to provide a low overhead and high performance interconnection based on PCIe, which supports global address space, user-level communication, and efficient communication primitives. Furthermore, the efficient sharing of I/O resource is another goal of this design. The prototype of the hyper-node controller is implemented in FPGA. The testing results show the lowest latency is only 1.242us and the highest bandwidth is 3.19GB/s, which is almost 99.7% of the theoretic peak bandwidth. |
Year | DOI | Venue |
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2013 | 10.1109/PDCAT.2013.25 | PDCAT |
Keywords | DocType | ISBN |
I/O resource sharing,communication primitives,parallel processing,global address space,hyper-node controller,latency,hypernode controller,user-level communication,resource allocation,system buses,PCIe,FPGA,large scale distributed computing system,direct memory access,high performance hyper-node hardware accelerator,field programmable gate arrays,input output virtualization,blade server,cHPP controller | Conference | 978-1-4799-2418-9 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Yong Su | 1 | 3 | 1.76 |
Feilong Liu | 2 | 429 | 15.52 |
Zheng Cao | 3 | 4 | 2.13 |
Zhan Wang | 4 | 7 | 4.66 |
Xiaoli Liu | 5 | 2 | 2.52 |
Xuejun An | 6 | 6 | 6.26 |
SUN Ning-Hui | 7 | 1268 | 97.37 |