Title
cHPP controller: A High Performance Hyper-node Hardware Accelerator
Abstract
The high-density blade server provides an attractive solution for the rapid increasing demand on computing. The degree of parallelism inside a blade enclosure nowadays has reach up to hundreds of cores. In such parallelism, it is necessary to accelerate communications inside a blade enclosure. However, commercial products seldom set foot in the optimization based on hardware. A hyper-node controller is proposed to provide a low overhead and high performance interconnection based on PCIe, which supports global address space, user-level communication, and efficient communication primitives. Furthermore, the efficient sharing of I/O resource is another goal of this design. The prototype of the hyper-node controller is implemented in FPGA. The testing results show the lowest latency is only 1.242us and the highest bandwidth is 3.19GB/s, which is almost 99.7% of the theoretic peak bandwidth.
Year
DOI
Venue
2013
10.1109/PDCAT.2013.25
PDCAT
Keywords
DocType
ISBN
I/O resource sharing,communication primitives,parallel processing,global address space,hyper-node controller,latency,hypernode controller,user-level communication,resource allocation,system buses,PCIe,FPGA,large scale distributed computing system,direct memory access,high performance hyper-node hardware accelerator,field programmable gate arrays,input output virtualization,blade server,cHPP controller
Conference
978-1-4799-2418-9
Citations 
PageRank 
References 
0
0.34
0
Authors
7
Name
Order
Citations
PageRank
Yong Su131.76
Feilong Liu242915.52
Zheng Cao342.13
Zhan Wang474.66
Xiaoli Liu522.52
Xuejun An666.26
SUN Ning-Hui7126897.37