Name
Abstract | ||
|---|---|---|
In this paper, we present a high throughput and low latency LDPC (low-density parity-check) decoder implementation on GPUs (graphics processing units). The existing GPU-based LDPC decoder implementations suffer from low throughput and long latency, which prevent them from being used in practical SDR (software-defined radio) systems. To overcome this problem, we present optimization techniques for a parallel LDPC decoder including algorithm optimization, fully coalesced memory access, asynchronous data transfer and multi-stream concurrent kernel execution for modern GPU architectures. Experimental results demonstrate that the proposed LDPC decoder achieves 316 Mbps (at 10 iterations) peak throughput on a single GPU. The decoding latency, which is much lower than that of the state of the art, varies from 0.207 ms to 1.266 ms for different throughput requirements from 62.5 Mbps to 304.16 Mbps. When using four GPUs concurrently, we achieve an aggregate peak throughput of 1.25 Gbps (at 10 iterations). |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/GlobalSIP.2013.6737137 | GlobalSIP |
Keywords | DocType | ISSN |
gpu systems,high throughput,ldpc codes,ldpc decoder,data communication,low latency,bit rate 1.25 gbit/s,parallel ldpc decoder,gpu,high throughput low latency ldpc decoding,codecs,decoding latency,algorithm optimization,graphics processing units,multistream concurrent kernel execution,optimization techniques,bit rate 62.5 mbit/s to 304.16 mbit/s,gpu-based ldpc decoder,asynchronous data transfer,sdr systems,bit rate 316 mbit/s,software radio,software-defined radio,coalesced memory access,parity check codes,gpu architectures,decoding | Conference | 2376-4066 |
Citations | PageRank | References |
28 | 1.28 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guohui Wang | 1 | 1088 | 60.78 |
| Michael Wu | 2 | 271 | 18.30 |
| Bei Yin | 3 | 212 | 14.61 |
| Joseph R. Cavallaro | 4 | 1175 | 115.35 |