Name
Title | ||
|---|---|---|
A hybrid erasure-coded ECC scheme to improve performance and reliability of solid state drives |
Abstract | ||
|---|---|---|
The high performance and ever-increasing capacity of flash memory has led to the rapid adoption of Solid-State Disks (SSDs) in mass storage systems. In order to increase disk capacity, multi-level cells (MLC) are used in the design of SSDs, but the use of such SSDs in persistent storage systems raise concerns for users due to the low reliability of such disks. In this paper, we present a hybrid erasure-coded (EECC) architecture that incorporates ECC schemes and erasure codes to improve both performance and reliability. As weak error-correction codes have faster decoding speed than complex error correction codes (ECC), we propose the use of weak-ECC at the segment level rather than complex ECC. To compensate the reduced correction ability of weak-ECC, we use an erasure code that is striped across segments rather than pages or blocks. We use a small sized HDD to store parities so that we can leverage parallelism across multiple devices and remove the parity updates from the critical write path. We carry out simulation experiments based on Disksim to demonstrate that our proposed scheme is able reduce the SSD average read-latency by up to 31.23% and along with tolerance from double chip failures, it dramatically reduces the uncorrectable page error rate. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/PCCC.2014.7017095 | Performance Computing and Communications Conference |
Keywords | Field | DocType |
error correction codes,flash memories,Disksim,MLC,SSD average read-latency,complex error correction codes,critical write path,double chip failures,flash memory,hybrid erasure-coded ECC scheme,hybrid erasure-coded architecture,mass storage systems,multilevel cells,parity updates,solid state drives,Erasure Code,Error Correction,Flash Memory,RAID-6,Reliability,SolidState Disk (SSD) | Flash memory,Computer science,Error detection and correction,Real-time computing,Chip,Decoding methods,Computer hardware,Erasure code,Mass storage,Erasure,Encoding (memory) | Conference |
ISSN | Citations | PageRank |
1097-2641 | 0 | 0.34 |
References | Authors | |
16 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pradeep Subedi | 1 | 27 | 3.83 |
| Ping Huang | 2 | 184 | 29.52 |
| Xubin He | 3 | 747 | 63.49 |
| Ming Zhang | 4 | 89 | 18.62 |
| Jizhong Han | 5 | 355 | 54.72 |