Name
Abstract | ||
|---|---|---|
In this work, we analyze efficient communication methods for a grid of many-core processors in the absence of cache coherence. For this study, we build a multi-chip processor with 240 tightly connected cores and demonstrate its scalability. This processor is based on the Intel SCC, a cluster-on-a-chip research processor with 48 non-coherent memory coupled cores. Our new research system virtually extends the on-chip network of multiple SCC systems and provides new communication functionality for direct on-chip memory access. We analyze access patterns of different communication schemes and apply techniques to hide latency, such as offloading communication and software caching with relaxed consistency. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2712386.2712393 | PMAM@PPoPP |
Keywords | Field | DocType |
cluster-on-a-chip,emulation of on-chip interconnect,low-level communication,message passing | Public records,Computer science,Latency (engineering),Chip,Software caching,Grid,Message passing,Embedded system,Scalability,Cache coherence | Conference |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pablo Reble | 1 | 60 | 6.32 |
| Stefan Lankes | 2 | 152 | 26.39 |
| Fabian Fischer | 3 | 28 | 3.39 |
| Matthias S. Müller | 4 | 463 | 57.74 |