Name
Abstract | ||
|---|---|---|
To achieve high performance, conventional superscalar processors maintain maximum front-end instruction delivery bandwidth, which is often suboptimal when program behavior and priority metrics change. This paper proposes an adaptive front-end throttling technique that dynamically adjusts the front-end instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. Circuit-level synthesis (45nm FreePDK) and simulation show that adaptive front-end throttling incurs negligible overhead but achieves average improvements of 7%, 28%, 28%, and 32% for performance, energy, energy-delay product, and energy-delay-squared product, respectively, over all benchmarks on an 8-way superscalar processor. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2627369.2627633 | ISLPED |
Keywords | Field | DocType |
adaptive hardware,energy,pipeline processors,adaptable architectures,instruction-level parallelism,low power,fetch throttling,instruction delivery,benchmark testing,measurement,optimization,hardware,pipelines | Front and back ends,Adaptive hardware,Pipeline transport,Program behavior,Computer science,Parallel computing,Real-time computing,Bandwidth (signal processing),Superscalar,Benchmark (computing),Bandwidth throttling,Embedded system | Conference |
ISSN | Citations | PageRank |
1533-4678 | 3 | 0.44 |
References | Authors | |
17 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhang Wei | 1 | 392 | 53.03 |
| Hang Zhang | 2 | 5 | 1.92 |
| John Lach | 3 | 1898 | 187.99 |