Name
Abstract | ||
|---|---|---|
Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on timing errors is characterized for a typical min-sum LDPC decoder architecture using circuit simulations. Failure modes are analyzed for arithmetic circuits performing variable and check node computations. It is shown that a rather unconventional register placement in the variable node unit is beneficial for voltage scaling, and that the check node unit may be designed such that only the least significant bits are more likely to experience errors. Insights into timing error characteristics obtained through this analysis can be used to estimate the limits of voltage scaling and associated energy saving in practical LDPC decoder designs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2627369.2627638 | ISLPED |
Keywords | Field | DocType |
voltage over-scaling,reliability, testing, and fault-tolerance,algorithms implemented in hardware,error-resilience,noisy decoder,arithmetic and signal processing circuits,advanced technologies,computation errors,registers,decoding,simulation | Telecommunications network,Computer science,Low-density parity-check code,Voltage,Timing error,Real-time computing,Electronic engineering,Decoding methods,Scaling,Ldpc decoding,Computation | Conference |
ISSN | Citations | PageRank |
1533-4678 | 2 | 0.36 |
References | Authors | |
14 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Behnam Sedighi | 1 | 58 | 10.33 |
| N. Prasanth Anthapadmanabhan | 2 | 33 | 6.43 |
| Dusan Suvakovic | 3 | 17 | 4.96 |