Name
Abstract | ||
|---|---|---|
Memory access tracing is one of the widely used methods to evaluate, analyze, and optimize hardware and software designs. We are developing a non-intrusive, scalable, full-address-range memory tracer. The tracer hardware board is compliant with the JEDEC DDR3 DIMM form factor, and fits in a DIMM slot. It is so compact that we can populate up to 16 tracer boards in a 4-CPU server chassis, and record the commands and addresses of all the memory accesses. Each board drives four SSDs to record the memory access addresses without a break until the SSDs are full. For example, we can make a trace of a full SPECjbb 2005 run, which lasts 26 minutes and generates over 11TB trace data. In addition to recording memory accesses, it collects various types of statistical data, such as a large number of segmented read/write statistics and DRAM bank utilization rates, and displays them on the control dashboard in real time. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1007/978-3-319-10696-0_20 | QUANTITATIVE EVALUATION OF SYSTEMS, QEST 2014 |
Keywords | Field | DocType |
memory trace, memory system, performance measurement | Dram,DIMM,Computer science,Theoretical computer science,Software,Chassis,Dashboard (business),Tracing,Operating system,Scalability | Conference |
Volume | ISSN | Citations |
8657 | 0302-9743 | 1 |
PageRank | References | Authors |
0.35 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nobuyuki Ohba | 1 | 28 | 5.80 |
| Seiji Munetoh | 2 | 327 | 33.14 |
| Atsuya Okazaki | 3 | 3 | 1.41 |
| Yasunao Katayama | 4 | 85 | 17.18 |