Name
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/GLSV.1994.289977 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
VLSI,circuit layout CAD,network routing,VLSI layout synthesis,gridless multi-layer area router,incremental routing,irregular rectilinear obstacles,layout cells,layout region,multiple nets,multiple pins,near optimal solutions,routing algorithms | Multipath routing,Link-state routing protocol,Equal-cost multi-path routing,Static routing,Computer science,Parallel computing,IC layout editor,Electronic engineering,Router,Routing table,Very-large-scale integration | Conference |
Citations | PageRank | References |
1 | 0.39 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naresh K. Sehgal | 1 | 2 | 1.64 |
| C.Y. Roger Chen | 2 | 3 | 1.09 |
| John M. Acken | 3 | 131 | 26.70 |