Paper Info
Title
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration.
Abstract
Growing demand to integrate more functionality into single-chip solutions require novel network-based interconnection models. The resulting increase in design complexity and strict time-to-market restrictions endanger the viability of Register Transfer Level (RTL) centric design processes in the future. To counteract these developments, the abstract design methodologies presented by Transaction Level Modeling (TLM 2.0/SystemC) are gaining popularity. With this paper, we demonstrate the benefits of raising the abstraction level by creating an adjustable Network on Chip (NoC) simulation model, satisfying the diverse needs of software and system engineers. Based on a proven and tested RTL NoC design, we applied modeling methods defined in the TLM 2.0 standard, creating flexible simulation model. It provides high timing accuracy, enabling precise behavioral and performance analysis. In addition, higher simulation speeds are achieved by adjusting the timing accuracy. The results demonstrate the advantages of variable simulation accuracy: simulation runs are accelerated by more than two orders of magnitude with performance and behavior assessment exposing a limited latency error of less than four clock cycles compared to the RTL model.
Year
DOI
Venue
2014
10.1145/2685342.2685349
NoCArc '14: International Workshop on Network on Chip Architectures Cambridge United Kingdom December, 2014
Keywords
Field
DocType
noc,simulation,tlm,abstraction
Computer architecture,Computer science,Latency (engineering),Transaction-level modeling,Network on a chip,Real-time computing,SystemC,Software,Register-transfer level,Abstraction layer,Interconnection,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4503-3064-0
2
0.40
References 
Authors
10
5
Name
Order
Citations
PageRank
Sven Alexander Horsinka130.77
Rolf Meyer241.47
Jan Wagner351.49
Rainer Buchty414318.44
Mladen Berekovic535243.38