Paper Info
Title
FPGA implementations of real-time detectors for a spectrally efficient FDM system
Abstract
A new method for detecting Spectrally Efficient Frequency Division Multiplexing (SEFDM) is proposed and verified through modelling and practical FPGA implementation. The method is derived through studies of two sphere decoding techniques, namely Fixed SD (FSD) with Sort-Free (SF) and Non-Sort-Free (NSF) algorithms. We report a co-simulation verification framework to verify the performance of these detectors and to choose an optimum design. Finally, a hybrid detector Truncated Singular Value Decomposition-Fixed Sphere Detector (TSVD-FSD) is tested on the FPGA platform. Error behaviour is studied for the practical FPGA system and then compared with theoretical/ideal modelling. Detailed analysis indicates the suitability of our design and implementation methods for SEFDM detection with 16 carriers and 25% bandwidth saving.
Year
DOI
Venue
2013
10.1109/ICTEL.2013.6632117
ICT
Keywords
Field
DocType
fixed sd,sefdm,fpga implementations,spectrally efficient fdm system,sphere decoding techniques,nsf algorithms,sfalgorithms,spectrally efficient frequency division multiplexing,real time detectors,nonsort free algorithms,truncated singular value decomposition,cosimulation verification framework,hybrid detector,sensors,error behaviour,tsvd-fsd,field programmable gate arrays,frequency division multiplexing,fixed sphere detector,decoding,throughput,real time systems,detectors
Singular value,Computer science,Frequency-division multiplexing,Field-programmable gate array,Real-time computing,Bandwidth (signal processing),Decoding methods,Throughput,Fpga implementations,Detector
Conference
ISBN
Citations 
PageRank 
978-1-4673-6425-6
3
0.42
References 
Authors
11
3
Name
Order
Citations
PageRank
Tongyang Xu1458.42
Ryan C. Grammenos2726.07
Izzat Darwazeh327340.03