Name
Abstract | ||
|---|---|---|
Memory controller design is challenging as real-time embedded systems feature an increasing diversity of real-time and non-real-time applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case execution time (WCET) of memory transactions must be provided to real-time applications, while the lowest possible average execution time must be given to the rest. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCET by sacrificing the average execution time, or are not scalable to directly support variable transaction sizes, or both. In this paper, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this paper are: 1) a back-end architecture for a real-time memory controller with a dynamic command scheduling algorithm, 2) a formalization of the timings of the memory transactions for the proposed architecture and algorithm, and 3) two techniques to bound the WCET of transactions with both fixed and variable sizes, respectively. We experimentally evaluate the proposed memory controller and compare both the worst-case and average-case execution times of transactions to a state-of-the-art semi-static approach. The results demonstrate that dynamic command scheduling outperforms the semi-static approach by 33.4% in the average case and performs at least equally well in the worst case. We also show the WCET is tight for transactions with fixed and variable sizes, respectively. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ECRTS.2014.18 | ECRTS |
Keywords | Field | DocType |
memory transactions,back-end architecture,scheduling,transaction size,dynamic command scheduling,storage management,average-case execution time,worst-case execution time,wcet,average execution time,realtime embedded systems,embedded systems,memory controller design,bismuth,dynamic scheduling,memory management,real time systems,worst case execution time | Interleaved memory,Computer science,Scheduling (computing),Parallel computing,Real-time computing,Two-level scheduling,Memory management,Dynamic priority scheduling,Database transaction,Memory controller,Scalability | Conference |
ISSN | Citations | PageRank |
1068-3070 | 19 | 0.68 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yonghui Li | 1 | 158 | 12.88 |
| Benny Akesson | 2 | 71 | 3.09 |
| Kees G. W. Goossens | 3 | 2050 | 131.83 |