Name
Abstract | ||
|---|---|---|
A transceiver architecture with multi-core software-defined radio (SDR) technology is proposed for the physical layer inner processing of IEEE 802.11p in intelligent transportation systems (ITS). By localizing the data transmissions between the adjacent digital signal processors (DSP), concatenate memories and concatenate buses are introduced to ease the bandwidth requirement for the data communication among multicores. The proposed transceiver architecture is verified by the electronic system-level (ESL) virtual platform with two application-specific instruction-set processors (ASIP). The high level power estimation results are also provided in this paper. To enhance of the channel estimation and equalization performance of IEEE 802.11p, the capability of the proposed architecture with the decision feedback algorithm is analyzed. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ITST.2012.6425181 | ITST |
Keywords | Field | DocType |
application-specific instruction-set processors,esl,decision feedback algorithm,data communication,ieee 802.11,data transmissions,traffic engineering computing,asip,dsp,software-defined radio technology,multicore sdr architecture,ieee 802.11p,digital signal processing chips,application-specific instruction-set processor (asip),smart vehicle systems,radio transceivers,software-defined radio (sdr),high level power estimation,automated highways,transceiver architecture,instruction sets,physical layer inner processing,channel estimation enhancement,software radio,intelligent transportation systems (its),its,concatenate buses,decision feedback equalisers,wireless lan,intelligent transportation systems,digital signal processors,concatenate memories,electronic system-level virtual platform,electronic system-level (esl),channel estimation,equalization performance enhancement | Digital signal processing,Computer science,Digital signal processor,Software-defined radio,Instruction set,Computer network,Communication channel,Physical layer,Intelligent transportation system,Multi-core processor | Conference |
ISBN | Citations | PageRank |
978-1-4673-3069-5 | 1 | 0.37 |
References | Authors | |
7 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yao-Hua Chen | 1 | 4 | 1.43 |
| Chia-Pin Chen | 2 | 1 | 0.37 |
| Pei-Wei Hsu | 3 | 1 | 0.37 |
| Chunfan Wei | 4 | 1 | 0.37 |
| Wei-Min Cheng | 5 | 1 | 0.37 |
| Hsun-Lun Huang | 6 | 1 | 0.37 |
| Tai-Yuan Cheng | 7 | 1 | 0.37 |
| Albert Chen | 8 | 10 | 2.37 |