Name
Title | ||
|---|---|---|
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems |
Abstract | ||
|---|---|---|
On-chip regulators are becoming increasingly important for ultra-low voltage nano-scale SoC systems. In this paper, an all-digital controlled linear regulator is presented. A novel Process-Voltage-Temperature (PVT) -aware design is implemented to mitigate environmental variations and to guarantee the resolution of the liner regulator. The proposed digital voltage regulator can achieve up to 98.4% current efficiency. This design leads to three major advantages: (1) fast response time of 60ns, (2) low quiescent current 162μA in a stable state, and (3) PVT tolerance. The settling time is about 138ns. The output voltage error in 0.3V stable states with error improvement of the resolution using PVT-aware DED is around 50%. The best FOM at the regulated voltage (VREG) of 0.51V is 4.2 pA·s. This digital controlled voltage regulator is designed and implemented for near-/sub- threshold operations. It can generate VREG from 0.3V ~ 0.51V in steps of 30mV without resolution degradation under PVT variations. The total area of the regulator is about 388.6×35.7μm2 using TSMC 65-nm low-power bulk CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SOCC.2014.6948914 | SoCC |
Keywords | Field | DocType |
low-power bulk cmos technology,ultra-low-power dvfs systems,cmos integrated circuits,current 162 mua,linear voltage regulator,size 65 nm,liner regulator,digital regulator,digital error detector,low-power electronics,voltage regulators,system-on-chip,pvt sensor,pvt compensation,process-voltage-temperature-aware design,nanoscale soc systems,time 60 s,pvt variation,voltage 0.3 v to 0.51 v,digital controlled voltage regulator design,soc systems,digital control | Regulator,Linear regulator,Settling time,Voltage,Electronic engineering,CMOS,Engineering,Low-dropout regulator,Voltage regulator,Dropout voltage | Conference |
Citations | PageRank | References |
3 | 0.52 | 3 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Chen Wu | 1 | 29 | 2.90 |
| Yi-Ping Kuo | 2 | 5 | 1.24 |
| Chung-Shiang Wu | 3 | 3 | 0.52 |
| Ching-Te Chuang | 4 | 3 | 0.52 |
| Yuan-Hua Chu | 5 | 99 | 38.56 |
| Wei Hwang | 6 | 254 | 44.40 |