Name
Abstract | ||
|---|---|---|
This paper proposed a low power CMOS flash-SAR ADC which consists of a flash ADC for 2 most significant bits and a SAR ADC with capacitor DAC for 8 least significant bits. Employment of a flash ADC allows the proposed circuit to enhance the conversion speed. The SAR ADC with a capacitor DAC provides a low power dissipation. The proposed ADC consumes 136 uW with a power supply of 1 V under a 0.18 um CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2 MHz. Therefore it results in 120 fJ/step of Figure of Merit (FoM). |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SOCC.2014.6948905 | SoCC |
Keywords | Field | DocType |
cmos process,low power,sar,power 136 muw,analogue-digital conversion,capacitor dac,successive approximation register,low-power electronics,figure of merit,flash adc,conversion speed,capacitors,sampling frequency,voltage 1 v,size 0.18 mum,low power cmos flash-sar adc,analog to digital converter,power supply,integrated circuit design,cmos digital integrated circuits,flip-flops,fom,analog-digital converter,digital-analogue conversion | Capacitor,Dissipation,Sampling (signal processing),Figure of merit,Effective number of bits,Flash ADC,CMOS,Electronic engineering,Engineering,Successive approximation ADC,Electrical engineering | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gi-Yoon Lee | 1 | 0 | 0.34 |
| Kwang-Sub Yoon | 2 | 0 | 2.37 |