Name
Title | ||
|---|---|---|
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications |
Abstract | ||
|---|---|---|
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as performance evaluation, speedup and bottleneck analysis, and system verification by taking the advantages of exploring many-core platforms in different abstraction levels altogether. To demonstrate our methodology, a design framework is proposed, consisting of a scalable many-core processor architecture and a hardware-independent software layer. Based on the scalable architecture, the prototype platform is also presented in Electronic System Level (ESL) and Register Transfer Level (RTL). The platform integrates sixteen Processing Elements (PEs) and a 4-by-4 mesh-based network with external memory. Our hardware-independent software layer aims at realistic parallel applications in the baremetal environment, i.e., without an Operating System (OS). With the on-chip communication library and system utilities, software built on top of the fast ESL many-core platform can be executed seamlessly on the RTL one. The analysis shows that our ESL simulation model provides relatively accurate performance metrics as compared with the RTL implementation, with up to 773.8 times faster in terms of simulation speed. In addition, we showcase the study of speedup and bottleneck analysis, which justifies the effectiveness of our methodology for embedded applications in many-core architectures. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SOCC.2014.6948942 | SoCC |
Keywords | Field | DocType |
parallel processing,processing elements,esl-rtl many-core platform,operating systems (computers),operating system,multiprocessing systems,electronic system level,register transfer level,os,embedded systems,embedded parallel applications,single-chip many-core architecture,parallel software development,mesh-based network,pe | Bottleneck,Computer architecture,Computer science,Electronic system-level design and verification,Software,Register-transfer level,Auxiliary memory,Speedup,Scalability,Embedded system,Microarchitecture | Conference |
Citations | PageRank | References |
2 | 0.45 | 7 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jyu-Yuan Lai | 1 | 61 | 4.21 |
| Chih-Tsun Huang | 2 | 673 | 54.07 |
| Ting-Shuo Hsu | 3 | 9 | 4.11 |
| Jing-Jia Liou | 4 | 552 | 64.27 |
| Tung-Hua Yeh | 5 | 2 | 0.45 |
| Liang-Chia Cheng | 6 | 2 | 0.45 |
| Juin-Ming Lu | 7 | 4 | 1.49 |