Name
Abstract | ||
|---|---|---|
As the flexibility offered by fine-grained field programmable gate array (FPGA) comes at a significant cost of area, speed, and power, there is a trend to use coarse-grained architecture (CGA) for dataflow applications requiring high computational resources. Existing CGA solutions are characterized according to the general organization, the processing element architecture, the basic interconnect structure and their reconfiguration characteristics. Based on the study of several digital signal processing (DSP) applications and their implemented VLSI architectures, we propose a CGA with parameterizable and flexible blocks based on a generic matrix and interconnected by a configurable network. The proposed architecture provides a good tradeoff between flexibility and performance-density. A CAD tool is developed to automate the implementation of the design on the architecture. A synthesizable VHDL code generator is also developed in order to further explore and validate the proposed architecture. The unification of coarse-grained logic block and bus-based interconnection bridges the gap between application-specific integrated circuit (ASIC) and CGA, resulting in area reduction from 40× to 6×, respectively. Experimental results demonstrate the performance and efficiency of the proposed architecture to implement DSP designs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SOCC.2014.6948927 | System-on-Chip Conference |
Keywords | Field | DocType |
VLSI,application specific integrated circuits,digital signal processing chips,field programmable gate arrays,hardware description languages,multiprocessor interconnection networks,program compilers,reconfigurable architectures,ASIC,CAD tool,CGA solutions,DSP applications,FPGA,VHDL code generator,VLSI architectures,application-specific integrated circuit,bus-based interconnection bridges,coarse-grained architecture,coarse-grained logic block,dataflow applications,digital signal processing applications,fine-grained field programmable gate array,flexible blocks,flexible reconfigurable architecture,generic matrix,parameterizable blocks,Coarse-grained architecture,DSP applications,FPGA,flexible,reconfigurable architecture | Computer architecture,Dataflow architecture,Computer science,Field-programmable gate array,Application-specific integrated circuit,Dataflow,Logic block,Reference architecture,VHDL,Reconfigurable computing,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdulfattah Mohammad Obeid | 1 | 14 | 7.26 |
| Syed Manzoor Qasim | 2 | 11 | 4.41 |
| Mohammed S. BenSaleh | 3 | 11 | 7.84 |
| Zied Marrakchi | 4 | 152 | 28.68 |
| Habib Mehrez | 5 | 200 | 39.21 |
| Heni Ghariani | 6 | 0 | 0.34 |
| Mohamed Abid | 7 | 42 | 11.08 |