Paper Info
Title
Shadow-scan design with low latency overhead and in-situ slack-time monitoring
Abstract
Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.
Year
DOI
Venue
2014
10.1109/ETS.2014.6847801
ETS
Keywords
Field
DocType
scan design,shadow-scan,in-situ slack-time monitoring,faster scan flip-flops,timing-critical paths,atpg,automatic test pattern generation,itc 99 benchmark circuits,fault diagnosis,logic design,online monitoring,stuck-at fault coverage,shadow-scan design,flip-flops,standard-scan cells,timing violations,automated test pattern generation,latency overhead,low latency overhead,logic testing,automated scan stitching,benchmark testing,logic gates
Boundary scan,Automatic test pattern generation,Fault coverage,Computer science,Latency (engineering),Scan chain,Real-time computing,Electronic engineering,Least slack time scheduling,Latency (engineering),Test compression
Conference
ISSN
Citations 
PageRank 
1530-1877
0
0.34
References 
Authors
6
7
Name
Order
Citations
PageRank
Sébastien Sarrazin131.09
Samuel Evain2736.98
Ivan Miro Panades3967.81
Alexandre Valentian400.34
Suresh Pajaniradja500.34
Lirida Alves de Barros Naviner6344.41
Valentin Gherman7363.35