Title
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli
Abstract
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.
Year
DOI
Venue
2014
10.1109/ATS.2014.30
ATS
Keywords
Field
DocType
post-silicon validation,integrated circuit testing,in-system application,constrained-random stimuli generator,automatic test pattern generation,post-silicon validation, constrained-random stimuli generator,post silicon validation stimuli,on-chip generation,user programmable constraints,sequential constraints,functionally-compliant stimuli,electronic engineering computing
System on a chip,Post-silicon validation,Computer science,Binary code,Electronic engineering,Real-time computing,Decoding methods,Silicon,Embedded system
Conference
ISSN
Citations 
PageRank 
1081-7735
3
0.41
References 
Authors
9
2
Name
Order
Citations
PageRank
Xiaobing Shi191.91
Nicolici, N.22099.28