Paper Info
Title
Automatic fault tree generation from SysML system models
Abstract
In this paper, a methodology is proposed to integrate safety analysis within a systems engineering approach. This methodology is based on SysML models and aims at generating (semi-) automatically safety analysis artifacts, mainly FMEA and FTA, from system models. Preliminary functional and component FMEA are automatically generated from the functional and structural models respectively, then completed by safety experts. By representing SysML structural diagram as a directed multi-graph, through a graph traversal algorithm and some identified patterns, generic fault trees are automatically derived with corresponding logic gates and events. The proposed methodology provides the safety expert with assistance during safety analysis. It helps reducing time and error proneness of the safety analysis process. It also helps ensuring consistency since the safety analysis artifacts are automatically generated from the latest system model version. The methodology is applied to a real case study, the electromechanical actuator EMA.
Year
DOI
Venue
2014
10.1109/AIM.2014.6878163
AIM
Keywords
Field
DocType
sysml,control engineering computing,directed graphs,electromechanical actuators,fault tolerant control,systems engineering,trees (mathematics),ema,fmea,fta,sysml structural diagram,sysml system models,automatic fault tree generation,directed multigraph,electromechanical actuator,failure mode effect analysis,logic events,logic gates,safety analysis,systems engineering approach,fault trees,reliability
Logic gate,Graph traversal,Computer science,Electromechanical actuator,Diagram,Fault tree analysis,Systems Modeling Language,System model,Reliability engineering
Conference
ISSN
Citations 
PageRank 
2159-6255
11
0.82
References 
Authors
8
3
Name
Order
Citations
PageRank
Faïda Mhenni1335.32
Nga Nguyen2132.90
Choley, J.-Y.3110.82