Name
Abstract | ||
|---|---|---|
Two countermeasures against DPA/CPA attacks have been designed, tested and compared on an AES encoding coprocessor implemented on FPGA. Both countermeasures are based on altering the clock signal and can be readily implemented at RTL design stage. Experimental results based on first order CPA attacks confirmed the effectiveness of both the countermeasures in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the encryption key can't be revealed by the relevant correlation peaks. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/MIXDES.2014.6872188 | MIXDES |
Keywords | Field | DocType |
clocks,coprocessors,cryptography,encoding,field programmable gate arrays,logic design,logic testing,aes encoding coprocessor,fpga,rtl design stage,sbox output,clock countermeasure,correlation power analysis attack,differential power analysis attack,encryption key,first order dpa-cpa attack,power curve acquisition,aes,cpa,clock random skewing,clock randomization,dpa,rtl countermeasure,side channel attack,correlation | Clock signal,Power analysis,First order,Computer science,Field-programmable gate array,Coprocessor,Key (cryptography),Encoding (memory),Embedded system | Conference |
Citations | PageRank | References |
2 | 0.41 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Menicocci, R. | 1 | 2 | 0.41 |
| Trifiletti, A. | 2 | 15 | 2.64 |
| Trotta, F. | 3 | 4 | 0.77 |