Name
Abstract | ||
|---|---|---|
The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary goals for the Haswell program are platform integration and low power to enable smaller form factors. Haswell incorporates several building blocks, including: platform controller hubs (PCHs), memory, CPU, graphics and media processing engines, thus creating a portfolio of product segments from fan-less Ultrabooks™ to high-performance desktop, as shown in Fig. 5.9.1. It also integrates a number of new technologies: a fully integrated voltage regulator (VR) consolidating 5 platform VRs down to 1, on-die eDRAM cache for improved graphics performance, lower-power states, optimized IO interfaces, an Intel AVX2 instruction set that supports floating-point multiply-add (FMA), and 256b SIMD integer achieving 2× the number of floating-point and integer operations over its predecessor. The 22nm process is optimized for Haswell and includes 11 metal layers (2 additional metal layers vs. Ivy Bridge [2]), high-density metal-insulator-metal (MIM) capacitors, and is tuned for different leakage/speed targets based on the market segment. For example, in some low-power products, the process is optimized to reduce leakage by 75% at Vmin, while paying only 12% intrinsic device degradation at the high-voltage corner. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISSCC.2014.6757361 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | DocType | ISSN |
dram chips,microprocessor chips,lower-power states,4th generation intel core processor,cpu,fma,haswell program,ia processors,intel avx2 instruction set,intel tri-gate process technology,ivy bridge,mim capacitors,pchs,simd integer,vr,fan-less ultrabooks,floating-point,floating-point multiply-add,fully integrated voltage regulator,graphics processing,high-density metal-insulator-metal capacitors,high-performance desktop,high-voltage corner,media processing engines,metal layers,on-die edram cache,optimized io interfaces,platform controller hub memory,size 22 nm,word length 256 bit | Conference | 0193-6530 |
Citations | PageRank | References |
9 | 1.33 | 0 |
Authors | ||
16 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nasser A. Kurd | 1 | 115 | 13.54 |
| Muntaquim Chowdhury | 2 | 48 | 4.54 |
| edward a burton | 3 | 9 | 1.67 |
| thomas p thomas | 4 | 9 | 1.67 |
| Christopher Mozak | 5 | 53 | 5.79 |
| brent boswell | 6 | 9 | 1.33 |
| manoj lal | 7 | 23 | 3.40 |
| anant deval | 8 | 14 | 2.20 |
| jonathan p douglas | 9 | 13 | 2.19 |
| mahmoud elassal | 10 | 9 | 1.33 |
| Ankireddy Nalamalpu | 11 | 22 | 2.97 |
| Timothy M. Wilson | 12 | 48 | 4.54 |
| matthew merten | 13 | 9 | 1.33 |
| Srinivas Chennupaty | 14 | 337 | 19.50 |
| wilfred gomes | 15 | 12 | 2.73 |
| Rajesh Kumar | 16 | 58 | 10.13 |