Name
Abstract | ||
|---|---|---|
We present an output stage design for high switching frequency DC-DC converters. The output stage comprises level-shifters, gate drivers, and power transistors. Gate drivers designed with the low voltage-swing method are evaluated against the standard full voltage-swing. Based on the simulation results, the gate drivers with the full voltage-swing results in higher power-efficiency and correspondingly, is employed in the output stage design. The output stage is designed using a 0.18 μm CMOS technology. The input pulse voltage to the output stage is 1.8 V and is level-shifted up to 3.3 V for a broad operational range of 0 to 3.3 V DC-DC conversions in portable applications. Simulation results show that at a switching frequency of 5 MHz and an output voltage of 1.65 V (50 % pulse duty cycle), the output stage delivers 300 mA current at a power efficiency of 89 %. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISICIR.2014.7029505 | ISIC |
Keywords | Field | DocType |
cmos integrated circuits,dc-dc power convertors,power transistors,cmos technology,dc-dc conversions,current 300 ma,gate drivers,high switching frequency dc-dc converters,input pulse voltage,level shifters,low voltage-swing method,voltage 1.8 v,voltage 3.3 v,low voltage-swing,output stage,switched-mode dc-dc converters,switches,simulation,logic gates,transistors | Electrical efficiency,Logic gate,0-10 V lighting control,Power semiconductor device,Duty cycle,Computer science,Converters,CMOS,Electronic engineering,Electrical engineering,Low-dropout regulator | Conference |
ISSN | Citations | PageRank |
2325-0631 | 0 | 0.34 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| tianshun ng | 1 | 0 | 0.34 |
| Yin Sun | 2 | 62 | 9.20 |
| victor adrian | 3 | 0 | 0.34 |
| bahhwee gwee | 4 | 0 | 0.34 |
| Joseph S. Chang | 5 | 292 | 79.39 |