Name
Title | ||
|---|---|---|
Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip |
Abstract | ||
|---|---|---|
This paper presents an accelerator-rich system-on-chip (SoC) architecture integrating many heterogeneous Coarse Grain Reconfigurable Arrays (CGRA) connected through a Network-on-Chip (NoC). The architecture is designed to maximize the reconfigurable processing capacity for the execution of massively parallel algorithms. The central node of the NoC contains a Reduced Instruction Set Computer (RISC) core that manages distribution of computing functions and data within the SoC while the other nodes contain CGRAs of application-specific sizes. Prior approaches coupled only a few accelerators with a RISC core using special instructions and/or a direct memory access device. In contrast, our design couples a RISC core to many CGRAs through the NoC. This approach provides for independent and simultaneous execution of multiple computing kernels. Furthermore, the proposed architecture mitigates power dissipation as CGRA sizes are tailored for the individual application kernels. We present a proof-of-concept design with a total of 408 reconfigurable processing elements. This instance and its sub-systems are customized and tested for different computationally-intensive signal processing algorithms. The overall single-chip computing system is synthesized for a Field Programmable Gate Array device. We present comparison to and evaluation against some of the existing multicore systems in terms of multiple performance metrics. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASAP.2014.6868647 | Application-specific Systems, Architectures and Processors |
Keywords | Field | DocType |
field programmable gate arrays,network-on-chip,reduced instruction set computing,CGRA,FPGA,NoC,RISC core,SoC,accelerator-rich architecture design,application-specific sizes,central node,computationally-intensive signal processing algorithms,direct memory access device,field programmable gate array device,massively parallel algorithms,multicore systems,multiple computing kernels,multiple heterogeneous coarse grain reconfigurable arrays,multiple performance metrics,network-on-chip,proof-of-concept design,reconfigurable processing capacity,reduced instruction set computer core,single-chip computing system,system-on-chip architecture | Computer architecture,Architecture,Dissipation,Computer science,Massively parallel,Instruction set,Parallel computing,Field-programmable gate array,Network on a chip,Real-time computing,Reduced instruction set computing,Direct memory access | Conference |
ISSN | Citations | PageRank |
2160-0511 | 5 | 0.43 |
References | Authors | |
13 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hussain, W. | 1 | 23 | 1.43 |
| Airoldi, R. | 2 | 12 | 1.38 |
| Hoffmann, H. | 3 | 8 | 1.01 |
| Ahonen, T. | 4 | 5 | 0.43 |