Name
Abstract | ||
|---|---|---|
Formal verification of specifications of digital devices, such as logical controllers, is an important part of the design process. Deadlock detection is one of the fundamental tasks of formal verification. There exist classical methods of deadlock detection in the concurrent discrete systems, which allow obtaining paths to every reachable deadlock without complete state space exploration. In the paper a method is proposed allowing further reduction of the size of explored state space during deadlock detection. The method is presented for the Petri nets. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/HSI.2014.6860480 | HSI |
Keywords | Field | DocType |
petri nets,concurrency control,formal verification,concurrent discrete systems,deadlock detection,digital devices,formal verifiaction,space exploration,solid modeling | Petri net,State space exploration,Computer science,Deadlock,Process architecture,Engineering design process,Deadlock prevention algorithms,State space,Distributed computing,Formal verification | Conference |
ISSN | Citations | PageRank |
2158-2246 | 2 | 0.40 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Karatkevich, A. | 1 | 3 | 0.75 |
| Grobelna, I. | 2 | 2 | 0.40 |