Title
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits
Abstract
This paper proposes multiple-clock multiple-edge-triggered multiple-bit flip-flops for designing simple and straight-forward asynchronous control circuits of the two-phase handshaking protocol. The proposed flip-flops have multiple clocks and multiple data inputs, and each data input can be stored in the flip-flop at both the rising edge and the falling edge of the corresponding clock. They can be applied in the asynchronous design of the two-phase handshaking protocol not only for synthesizing simple control circuits, but also for obtaining robust circuits. The performance of the proposed flip-flops have been evaluated using the PTM 22 nm HP device parameters.
Year
DOI
Venue
2014
10.1109/ISCAS.2014.6865085
Circuits and Systems
Keywords
Field
DocType
asynchronous circuits,clocks,flip-flops,logic design,protocols,asynchronous circuits,asynchronous design,multiple clock multiple-edge-triggered multiple bit flip-flops,size 22 nm,two-phase handshaking protocol
Asynchronous communication,Multiple data,Asynchronous system,FLOPS,Computer science,Electronic engineering,Handshaking,Electronic circuit,Signal edge,Asynchronous circuit
Conference
ISSN
Citations 
PageRank 
0271-4302
2
0.39
References 
Authors
5
2
Name
Order
Citations
PageRank
Masashi Imai1367.63
Tomohiro Yoneda235341.62