Name
Abstract | ||
|---|---|---|
Disparity estimation is a common task in stereo vision and usually requires a high computational effort. High resolution disparity maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3D glasses. In this paper, an FPGA architecture for a disparity estimation algorithm is proposed, that is capable of processing high-definition content in real-time. The resulting architecture is efficient in terms of power consumption and can be easily scaled to support higher resolutions. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCE.2014.6780927 | Consumer Electronics, IEEE Transactions |
Keywords | Field | DocType |
field programmable gate arrays,high definition video,image resolution,stereo image processing,three-dimensional displays,FPGA architecture,autostereoscopic displays,computational effort,field programmable gate arrays,full HD real time disparity estimation algorithm,hardware implementation,high resolution disparity maps,image quality,stereo content,stereo vision,FPGA,L-HRM,disparity estimation,stereo matching | Computer science,Stereopsis,Image quality,Real-time computing,Artificial intelligence,Throughput,Power consumption,Computer vision,Architecture,Algorithm design,Algorithm,Autostereoscopy,Image resolution | Journal |
Volume | Issue | ISSN |
60 | 1 | 0098-3063 |
Citations | PageRank | References |
10 | 0.53 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Werner | 1 | 10 | 0.53 |
| Benno Stabernack | 2 | 13 | 0.93 |
| Christian Riechert | 3 | 10 | 0.53 |