Name
Abstract | ||
|---|---|---|
In circuit design and evaluation, power and delay play a major role in deciding the circuit performance. Power and delay are approximately inversely related to each other and if one parameter is decreased the other gets increased. The proposed method uses power-delay-product (PDP) as performance metric to optimize the delay and power. The mathematical model has been developed to minimize the PDP by sizing the gates in a chain of inverters and NAND-NOR-INV combinational circuit. The results are validated using TSMC 0.18μm, 1.8V CMOS technology in mentor graphics' ELDO Spice. A significant reduction in power 11% and 27% for 3 and 5 stages respectively has been observed with a small increment in delay of 2% and 11%. Similarly, for NAND-NOR-INV circuit a reduction of approximately 14% in power with a minute change in delay has been observed. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICACCI.2014.6968530 | Advances in Computing, Communications and Informatics |
Keywords | DocType | Citations |
CMOS logic circuits,NAND circuits,NOR circuits,combinational circuits,logic design,logic gates,ELDO Spice mentor graphics,NAND-NOR-INV combinational circuit,PDP optimization,TSMC CMOS technology,circuit design,gate sizing,inverters,logical effort,mathematical model,power-delay-product optimization,size 0.18 mum,voltage 1.8 V,PDP minimization,logical effort,optimization,power-delay-product,sizing | Conference | 0 |
PageRank | References | Authors |
0.34 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sachin Maheshwari | 1 | 0 | 0.34 |
| Jimit Patel | 2 | 0 | 0.34 |
| Sumit K. Nirmalkar | 3 | 0 | 0.34 |
| Anu Gupta | 4 | 8 | 3.99 |