Paper Info
Title
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning
Abstract
Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.
Year
DOI
Venue
2014
10.1109/IPDPSW.2014.41
Parallel & Distributed Processing Symposium Workshops
Keywords
Field
DocType
checkpointing,circuit layout,field programmable gate arrays,minimisation,network analysis,radiation hardening (electronics),FPGAs,MTTR minimization,SEU mitigation,Xilinx SEM IP core,automatic netlist partitioning,bitstream,checkpointing,circuit analysis technique,datapath-intensive circuits,floorplanning,mean-time-to-repair minimization,optimization methodology,scrubbing effort minimization,single event upset mitigation
Netlist,Control theory,Computer science,Parallel computing,Circuit design,Field-programmable gate array,Network analysis,Bitstream,Electronic circuit,Floorplan
Conference
Citations 
PageRank 
References 
2
0.37
9
Authors
3
Name
Order
Citations
PageRank
Bernhard Schmidt121.04
Daniel Ziener220.37
Jürgen Teich3243.69